The invention relates generally to circuit chip packaging. In one form of high density interconnect (HDI) circuit module, an adhesive-coated polymer film overlay is applied over a substrate which can support integrated circuit chips in chip wells. Via openings are then formed to expose chip pads of the integrated circuit chips. The polymer film provides an insulated layer upon which is deposited a metallization pattern for interconnection of substrate metallization and/or individual circuit chips through the vias. Methods for performing an HDI process using overlays are further described in Eichelberger et al., U.S. Pat. No. 4,783,695, issued Nov. 8, 1988, and in Eichelberger et al., U.S. Pat. No. 4,933,042, issued Jun. 12, 1990. Generally a plurality of polymer film overlays and metallization patterns are used.
In another form of circuit module fabrication (referred to herein as chip on flex), as described by Cole et al., U.S. Pat. No. 5,527,741, issued Jun. 18, 1996, a method for fabricating a circuit module includes using a flexible interconnect layer having a metallized base insulative layer and an outer insulative layer. At least one circuit chip having chip pads is attached to the base insulative layer and vias are formed in the outer and base insulative layers to expose selected portions of the base insulative layer metallization and the chip pads. A substrate can be molded around the attached chip or chips. A patterned outer metallization layer is applied over the outer insulative layer extending through selected ones of the vias to interconnect selected ones of the chip pads and selected portions of the base insulative layer metallization. The concept of a pre-metallized flexible interconnect layer was extended as described by commonly assigned Saia et al., U.S. Pat. No. 5,874,770, wherein a method for fabricating a flexible interconnect film includes applying a resistor layer over one or both surfaces of a dielectric film; applying a metallization layer over the resistor layer; applying a capacitor dielectric layer over the metallization layer; and applying a capacitor electrode layer over the capacitor dielectric layer. The capacitor electrode layer is patterned to form a first capacitor electrode; the capacitor dielectric layer is patterned; the metallization layer is patterned to form a resistor; and the metallization layer and the resistor layer are patterned to form an inductor and a second capacitor electrode.
The chip on flex embodiments have been used to fabricate both single chip and multichip modules and represent a simplification of the earlier HDI processes. A drawback remains however due to the fact that the associated fabrication equipment and processes are not normally found in conventional contract component assembly facilities. For example, contract assemblers generally do not form vias or apply and pattern metal and may not be willing to invest in the equipment required for such steps, particularly in light of associated waste products and environmental regulations.
Therefore, it would be desirable to have a circuit chip package fabrication technique that is simpler for a contract component assembler to apply.
In one embodiment of the present invention the via formation is eliminated while in other embodiments metallization and patterning steps are additionally eliminated. These techniques, which can be used for single chip or multi-chip packages, offer the performance advantages of chip on flex with reduced equipment and processing step requirements and with less environmental concerns.
One method for packaging at least one circuit chip includes: providing an interconnect layer including insulative material having a first side and a second side, initial metallization patterned on second side metallized portions of the second side and not on second side non-metallized portions of the second side, at least one substrate via extending from the first side to one of the second side metallized portions, and at least one chip via extending from the first side to one of the second side non-metallized portions; positioning the at least one circuit chip on the second side with at least one chip pad of the at least one circuit chip being aligned with the at least one chip via; and patterning connection metallization on selected portions of the first side of the interconnect layer and in the vias so as to extend to the at least one second side metallized portion and to the at least one chip pad. In related embodiments vias are pre-metallized and coupled to chip pads of the circuit chips by an electrically conductive binder.